The present invention relates to computer systems of the kind that allow peripheral devices to be plugged in and dynamically configured while the computer is running, more especially to the handling of interrupts generated by such peripheral devices.
Current personal computers (PC""s) are designed to allow peripheral devices to be connected to the main system hardware.
One kind of bus for connecting peripheral devices is the Industry Standard Architecture (ISA) bus. The ISA bus is an older design of medium speed computer bus which has been in use since the 1980""s and is still present on most current IBM compatible personal computers.
Another, more modern, kind of bus is defined by the Personal Computer Memory Card International Association (PCMCIA). Peripheral devices conforming to this standard are sometimes referred to as PCMCIA cards. The PCMCIA standard has been implemented in the form of a medium speed computer bus designed to allow miniature peripheral devices to be plugged into laptop and desktop computers, for example: modems, storage devices etc.
The PCMCIA bus is electrically similar to an ISA bus, but has the additional functionality of allowing dynamic configuration of a PCMCIA card by the PC as it is plugged in. This means that the computer does not have to be turned off to add new hardware in the form of a PCMCIA card. This capability is sometimes referred to using the terms xe2x80x9chot-insertionxe2x80x9d and xe2x80x9cplug-n-playxe2x80x9d. An automatic resource allocation and configuration process is effected by software and is invoked when a new piece of PCMCIA compliant hardware is detected by the PC. This process is designed to simplify hardware installation from the end-user""s point of view.
Although PCMCIA cards are in widespread use and offer the advantage of a dynamic insertion capability, a problem arises when external PCMCIA cards are connected to a peripheral component interconnect (PCI) bus of a PC through a PCI-to-PCMCIA bridge, as will be described further below.
A PCI bus is the main system bus in many current PC""s. A PCI bus is a high speed bus that can be used to transfer data and commands around the PC motherboard and beyond. The PCI bus standard provides four possible PCI interrupt signals; INTA#, INTB#, INTC# and INTD#, referred to generically as INTX#. A xe2x80x9ctypicalxe2x80x9d add-in PCI board will have only one function and will, by convention, only connect to INTA#. INTB# through INTD# are intended for additional optional functions on the same board and are used by so-called multi-function PCI boards. For example, a board that offers three distinct functions would connect INTA# to the first function, INTB# to the second and INTC# to the third.
A bridge is a generic two-port or multi-port device which connects to a PCI bus on one xe2x80x9csidexe2x80x9d and to another bus, on the other xe2x80x9csidexe2x80x9d. The other bus can itself be a PCI bus, but equally it can be of any other type, for example a PCMCIA bus. A bridge serves to expand or extend the PCI bus system without violating the fundamental electrical parameters that define the PCI bus.
One function performed by a PCI-to-PCMCIA bridge is to map an input interrupt signal to one of sixteen outputs, corresponding to the legacy interrupt channels (LICs) which formed part of the ISA bus and that are implemented in current IBM compatible PC""s. Interrupt mapping is the logical connection of an interrupt signal to one of the system""s available LICs. The association is made by configuration of the bridge""s hardware to direct the interrupt signal to the required LIC hardware line. The LICs are named IRQ0 to IRQ15 inclusive and originated from early IBM compatible PC""s that used 8259 type interrupt controller chips. It is noted that due to the one-to-one correspondence between LICs and the interrupts used as part of the ISA bus, LICs are often referred to as xe2x80x9cISA interruptsxe2x80x9d. The LICs are distributed out among the system""s internal and external peripheral devices, usually with each device being mapped to one LIC.
Each PCMCIA device can use a single interrupt and that interrupt is dynamically allocated to the PCMCIA device on installation by the operating system. The mapping is used to configure the bridge hardware and is also stored in the operating system""s own internal configuration tables. Subsequently, the application software can obtain the LIC mapping from the operating system to determine the LIC that the PCMCIA card has been mapped to. The application software is thus able to register itself as an interrupt handler for the relevant LIC. The interrupt allocation is performed dynamically based on which LICs are currently free and what resource requirements other devices in the system may have. It is important to emphasize that the mapping is not fixed. It can change freely. For example, the operating system may allocate the same PCMCIA card LIC channel IRQ12 on one day and IRQ11 on the next day.
For a PCI-to-PCI bridge, all relevant interrupt signals are passed through the bridge. However, for a PCI-to-PCMCIA bridge connected via a PCI expansion connector, this is not the case. As a result software failure can occur when PCMCIA cards are plugged into an adapter device that uses a PCI-to-PCMCIA bridge connected to a PCI expansion connector. This situation is now described with reference to FIG. 1 of the accompanying drawings.
FIG. 1 shows a PCMCIA card 10 that is connected, or plugged into, a PCI-to-PCMCIA bridge 20 that is in turn connected to, or plugged into, a PCI expansion connector 30 of a PC by a corresponding bridge PCI expansion connector 29 that includes pins for the PCI bus data, and address and control lines 40, and the PCI interrupt lines 25 to 28. Certain internal components of the PC that are relevant to interfacing with the PCI expansion connector 30 are also shown, these components being labeled with reference numerals in the range 40 to 60.
The PC components illustrated are the PCI interrupt channel connections INTX# 41 to 44, and the PCI bus 40. The PCI bus 40 is connected to the main system PCI bus of the PC. The PCI interrupt channel connections 41 to 44 connect to respective demultiplexers 56 to 59 which serve to map the respective four PCI interrupts to their allocated LIC 60 for conveying IRQ0 . . . 15 between a programmable interrupt controller (PIC) 50 and the PC""s peripheral devices, of which the illustrated PCI expansion connector 30 is but one. The demultiplexers 56 to 59 are components of system board PCI interrupt mapping circuitry 55.
The sixteen LICs 60 are connected to the programmable interrupt controller (PIC) 50. A PIC is a device that prioritizes and multiplexes the 16 LICs and sends an interrupt request to the processor for each LIC that is in an active state. Typical IBM compatible computers use two Intel 8259 PICs (or compatible) in cascade. Moreover, it is noted that the PCI interrupts once mapped to LICs are handled slightly differently from ISA-type interrupts since the PCI interrupts are level sensitive whereas the ISA-type interrupts are edge sensitive.
An interrupt sent to the processor by the PIC 50 constitutes an interrupt request to alert the processor that a device requires servicing by software. The interrupt is sent (or asserted) to the PIC using either an INTX# signal, or on the LIC interconnects 60 using an IRQ0 . . . 15, and then from the PIC to the processor on a dedicated processor signal line (not shown) using an INTX# signal, or on the LIC interconnects 60 using an IRQ0 . . . 15 signal. The interrupt request is then handled by the processor calling an appropriate interrupt servicing routine (ISR) in system software.
The PCMCIA card 10 has an interface including a single interrupt 12. In order for the interrupt 12 to be usable by the PC, the interrupt 12 is mapped to one of the LICs of the PC. This mapping process is done by a routing circuit in the form of a demultiplexer 24 controlled by a controller 22 that in combination direct the PCMCIA interrupt 12 to any one of the bridge LIC outputs 35. The controller 22 includes a register 23 that is addressable by the PC. The register 23 is used to store the LIC currently allocated to the PCMCIA card 10 by the PC. The allocated LIC is written to the control circuit register by the PC""s processor. In addition, the system software maintains a LIC mapping record for all LICs, for example in the form of a table, in which the LIC to which the PCMCIA interrupt 12 is mapped will also be stored.
Although the bridge device 20 has connections 35 for each of the LICs, these are only useful when the bridge 20 is built onto the system board of the computer and the LICs can be physically wired up to the system""s PIC 50. This would be possible for an internal PCI-to-PCMCIA bridge such as would be found in a laptop PC equipped with PCMCIA slots. However, for an adapter board using a PIC-to-PCMCIA bridge and plugged into a PCI expansion connector 30 on a desktop PC or other system with PCI expansion connectors, there is no connection from the bridge LIC connections 35 through to the PC.
The lack of connection between the bridge LIC connections 35 and the PC""s internal LIC interconnects 60 means that any interrupt output on the LIC connections 35 from the bridge 20 is lost and will never reach the PIC 50.
On the one hand, the operating system is free to configure a PCI-to-PCMCIA bridge 20 to map the PCMCIA interrupt 12 to one of the LICs, since the bridge controller 22 is still freely addressable through the PCI bus.
On the other hand, the system is liable to software failure at any time, since none of the LIC bridge connections 35 are physically connected to the PC. For example, if software were to assign the PCMCIA card 10 to IRQ12 and configure the bridge hardware accordingly, then this interrupt would never reach the PIC 50 so that no interrupt request would ever get through to the processor. This in turn will mean that any application software that is waiting to receive interrupt requests on IRQ12 will never be alerted that the card 10 requires servicing and so the card and software will not work properly together.
In summary, although a PCMCIA card can be plugged into a PCI expansion connector through a PCI-to-PCMCIA bridge, immediate or sporadic software failure will result. What is needed is hardware or software, or a combination of both, that allows reliable operation of a computer system when a PCMCIA card is plugged into a PCI expansion connector through a PCI-to-PCMCIA bridge.
Here it is noted that the above-described problem does not occur with ISA-to-PCMCIA bridge devices, because on an ISA bus all free LICs are physically wired to the ISA expansion connector, thus providing direct electrical connection to the LICs that are wired inside the computer to an 8259-compatible PIC device.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features of the dependent claims may be combined with those of the independent claims as appropriate and in combinations other than those explicitly set out in the claims.
According to a first aspect of the invention there is provided a computer system having a PCI expansion connector and further including:
an operating system operable to detect a PCI-to-PCMCIA bridge on the PCI expansion connector and in response thereto to allocate a legacy interrupt channel for interrupts originating from the PCI-to-PCMCIA bridge, and also operable to detect connection of a PCMCIA card to the PCI-to-PCMCIA bridge and in response thereto to allocate a further legacy interrupt channel for interrupts originating from the PCMCIA card; and
a device driver for a PCI-to-PCMCIA bridge, the device driver including a trap mechanism operable to intercept PCI interrupts received through the PCI expansion connector and, in response to interception of a PCI interrupt, to call an interrupt management routine operable to determine if the PCI interrupt was generated by the PCMCIA card and, if so, to call an interrupt service routine using the PCMCIA card""s allocated legacy interrupt channel as an operand.
The computer system of the first aspect of the invention is suitable for receiving a PCI-to-PCMCIA bridge, the bridge being connected to the computer system""s PCI expansion connector. The bridge can be connected to the computer system""s PCI expansion connector by a corresponding PCI expansion connector. The bridge may include a PCI interrupt pin for transmitting a PCI interrupt to a corresponding pin on the first mentioned PCI expansion connector; a PCMCIA connector for connecting to a PCMCIA card, the PCMCIA connector including a PCMCIA interrupt pin for receiving PCMCIA interrupts; and an interrupt converter arranged to convert PCMCIA interrupts received at the PCMCIA interrupt pin into PCI interrupts and to supply said PCI interrupts to the PCI interrupt pin of the PCI expansion connector.
According to a further aspect of the invention there is provided a method of handling an interrupt in a computer system including a PCI expansion connector, the method comprising:
(a) sensing a PCI-to-PCMCIA bridge on the PCI expansion connector;
(b) loading a device driver for the PCI-to-PCMCIA bridge, the device driver including an interrupt service routine for handling PCMCIA interrupts;
(c) allocating a legacy interrupt channel to the PCMCIA interrupts;
(d) detecting a PCMCIA interrupt; and
(e) calling the interrupt service routine using the legacy interrupt channel allocated to PCMCIA interrupts as an operand.
The method may further comprise the steps of: (f) disabling detection of further PCMCIA interrupts after step (d) and before step (e); and (g) re-enabling detection of further PCMCIA interrupts after step (e).
According to another aspect of the invention, there is provided a device driver for handling interrupts from an external peripheral device in a computer system including a programmable interrupt controller (PIC) connected to receive interrupts on a plurality of legacy interrupt channel connections and including status registers for receiving read and write accesses relating to pending interrupts and returning an access result.
The device driver of this aspect of the invention is operable to handle interrupts from an external peripheral device that is connected to a peripheral connector of a computer system and that has an interrupt line that can be allocated a legacy interrupt channel, but is not connected in hardware to one of said legacy interrupt channel connections of the computer system. The device driver includes a PIC emulation routine operable to modify said access result for read accesses to at least one of said status registers so that the access result is returned in a state which it would have if said interrupt line of the external peripheral device were supplied in hardware to the PIC on that one of said legacy interrupt channel connections corresponding to the legacy interrupt channel allocated to the external peripheral device.
The device driver may be operable with a PIC in which one of said status registers is an in-service register for indicating an active one of any of said pending interrupts and wherein the PIC additionally comprises a command register. In this case, the PIC emulation routine is operable to set an in-service bit of said access result for read accesses to the in-service register when the previous write access to the command register was a command to access the in-service register.
Additionally, the PIC emulation routine may be operable to configure a debug register of a processor to trap read and write accesses to addresses within an address range including at least one of said status registers and, on trapping, to call a trap function for controlling interaction of the read and write accesses with the PIC.
Further aspects of the invention provide a carrier medium bearing the device driver. The carrier medium may be a transmission medium, such as an optical fiber, metal cable or carrier wave. The carrier medium may also be a recording medium, such as a magnetic storage device, an optical storage device, a read-only-memory (ROM) or other non-volatile memory.
Still further aspects of the invention are exemplified by the attached claims.
The various aspects of the invention thus provide a modified PCI-to-PCMCIA bridge together with a device driver for the bridge that allow reliable operation of a PCMCIA card plugged into a PCI expansion connector through the modified PIC-to-PCMCIA bridge.